/*
 * timer-ss805x-pre.h
 *
 * The precompile definitions for timer-ss805x.c.
 * Under normal conditions, it CAN be ignored by reader.
 *
 * Copyright (C) 2024 Sinh Micro, Inc.
 * Subject to the GNU Public License, version 2.
 *
 * Author: lixiang<lixiang@sinhmicro.com>
 * 
 * Encoding format: GB2312
 * Version: v1.2.2
 * Date: 2024-11-05
 */

#ifndef __TIMER_SS805X_PRE_H__
#define __TIMER_SS805X_PRE_H__

#include "hal-config.h"
#include "system.h"

#if (CONFIG_USING_TIMER0 == 1)
    #define TIMER0_VAL_PRE    (SYS_SCLK_FREQ / CONFIG_TIMER0_OVERFLOW_RATIO) 

    #if (TIMER0_VAL_PRE * CONFIG_TIMER0_OVERFLOW_RATIO != SYS_SCLK_FREQ)
        #warning CONFIG_TIMER0_OVERFLOW_RATIO Can not be divided,   \
                 exist accuracy error! 
    #endif

    #if (CONFIG_TIMER0_MODE < 2)
        #error("invalid CONFIG_TIMER0_MODE")
    #endif

    #if (CONFIG_TIMER0_MODE == 2)
        #if (TIMER0_VAL_PRE > 8388480UL) /*128 * 65535*/
            #error CONFIG_TIMER0_OVERFLOW_RATIO not suitable, please adjust! 
        #endif

        #if (CONFIG_TIMER0_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 &&         \ 
             CONFIG_TIMER0_OVERFLOW_RATIO <= SYS_SCLK_FREQ)
            #define TIMER0_DIV_VAL_PRE (1)
            #define TIMER0_DIV_VAL (0)
        #elif (CONFIG_TIMER0_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 2 &&   \ 
               CONFIG_TIMER0_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 2)
            #define TIMER0_DIV_VAL_PRE (2)
            #define TIMER0_DIV_VAL (1)
        #elif (CONFIG_TIMER0_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 4 &&   \
               CONFIG_TIMER0_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 4)
            #define TIMER0_DIV_VAL_PRE (4)
            #define TIMER0_DIV_VAL (2)
        #elif (CONFIG_TIMER0_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 8 &&   \ 
               CONFIG_TIMER0_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 8)
            #define TIMER0_DIV_VAL_PRE (8)
            #define TIMER0_DIV_VAL (3)
        #elif (CONFIG_TIMER0_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 16 &&  \
               CONFIG_TIMER0_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 16)
            #define TIMER0_DIV_VAL_PRE (16)
            #define TIMER0_DIV_VAL (4)
        #elif (CONFIG_TIMER0_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 32 &&  \
               CONFIG_TIMER0_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 32)
            #define TIMER0_DIV_VAL_PRE (32)
            #define TIMER0_DIV_VAL (5)
        #elif (CONFIG_TIMER0_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 64 &&  \
               CONFIG_TIMER0_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 64)
            #define TIMER0_DIV_VAL_PRE (64)
            #define TIMER0_DIV_VAL (6)
        #elif (CONFIG_TIMER0_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 128 && \
               CONFIG_TIMER0_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 128)
            #define TIMER0_DIV_VAL_PRE (128)
            #define TIMER0_DIV_VAL (7)
        #endif

        #define TIMER0_RELOAD_VALUE (65536 - TIMER0_VAL_PRE /   \
                                     TIMER0_DIV_VAL_PRE)
    #else
        #error timer0 mode is inappropriate.
    #endif
    
    #define TCON1_VAL_TIMER0    ((TCON1 & 0xF8) | TIMER0_DIV_VAL)
#endif

#if (CONFIG_USING_TIMER2 == 1)
    #define TIMER2_VAL_PRE    (SYS_SCLK_FREQ / CONFIG_TIMER2_OVERFLOW_RATIO) 

    #if (TIMER2_VAL_PRE * CONFIG_TIMER2_OVERFLOW_RATIO != SYS_SCLK_FREQ)
        #warning CONFIG_TIMER2_OVERFLOW_RATIO Can not be divided,   \
                 exist accuracy error! 
    #endif

    #if (CONFIG_TIMER2_MODE < 2)
        #error("invalid CONFIG_TIMER2_MODE")
    #endif
    
    #if (CONFIG_TIMER2_MODE == 2)
        #if (TIMER2_VAL_PRE > 8388480UL) /*128 * 65535*/
            #error CONFIG_TIMER2_OVERFLOW_RATIO not suitable, please adjust! 
        #endif

        #if (CONFIG_TIMER2_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 &&          \
             CONFIG_TIMER2_OVERFLOW_RATIO <= SYS_SCLK_FREQ)
            #define TIMER2_DIV_VAL_PRE (1)
            #define TIMER2_DIV_VAL (0)
        #elif (CONFIG_TIMER2_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 2 &&    \
               CONFIG_TIMER2_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 2)
            #define TIMER2_DIV_VAL_PRE (2)
            #define TIMER2_DIV_VAL (1)
        #elif (CONFIG_TIMER2_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 4 &&    \
               CONFIG_TIMER2_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 4)
            #define TIMER2_DIV_VAL_PRE (4)
            #define TIMER2_DIV_VAL (2)
        #elif (CONFIG_TIMER2_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 8 &&    \
               CONFIG_TIMER2_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 8)
            #define TIMER2_DIV_VAL_PRE (8)
            #define TIMER2_DIV_VAL (3)
        #elif (CONFIG_TIMER2_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 16 &&   \
               CONFIG_TIMER2_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 16)
            #define TIMER2_DIV_VAL_PRE (16)
            #define TIMER2_DIV_VAL (4)
        #elif (CONFIG_TIMER2_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 32 &&   \
               CONFIG_TIMER2_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 32)
            #define TIMER2_DIV_VAL_PRE (32)
            #define TIMER2_DIV_VAL (5)
        #elif (CONFIG_TIMER2_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 64 &&   \
               CONFIG_TIMER2_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 64)
            #define TIMER2_DIV_VAL_PRE (64)
            #define TIMER2_DIV_VAL (6)
        #elif (CONFIG_TIMER2_OVERFLOW_RATIO >= SYS_SCLK_FREQ / 65536 / 128 &&  \
               CONFIG_TIMER2_OVERFLOW_RATIO <= SYS_SCLK_FREQ / 128)
            #define TIMER2_DIV_VAL_PRE (128)
            #define TIMER2_DIV_VAL (7)
        #endif

        #define TIMER2_RELOAD_VALUE (65536 - TIMER2_VAL_PRE /    \
                                     TIMER2_DIV_VAL_PRE)
        #else
            #error timer2 mode is inappropriate.
    #endif

    #define TCON0_VAL_TIMER2    ((TCON0 & 0x1f) | (TIMER2_DIV_VAL << 5))
#endif

#endif
